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INTEGRATED CIRCUITS
DATA SHEET
TDA8041H Quadrature demodulator controller
Preliminary specification File under Integrated Circuits, IC03 November 1994
Philips Semiconductors
Philips Semiconductors
Preliminary specification
Quadrature demodulator controller
FEATURES * Generates all control signals for Quadrature Phase-Shift Keying (QPSK) and Binary Phase-Shift Keying (BPSK) demodulation * Can be used in applications with low Eb/No and high symbol rate (up to 30 x 106 symbols/s) * Digital I and Q outputs (3 bits) for soft decision within error correction * Two matched analog-to-digital converters to quantize the I and Q signals * A digital detector for each control loop to generate the required control signals * Digital-to-analog converters and operational amplifiers to allow high flexibility for loop time constants * Special input stage to interface with the voltage controlled crystal oscillator * Positive 5 V supply voltage. QUICK REFERENCE DATA SYMBOL VDD(A) VDDA(C) VDD(I/O) VDDD VDD(C) IDD(tot) VIQ Rsym IO(DAC) PARAMETER supply voltage for operational amplifiers (pin 5) analog supply voltage for converters (pin 20) supply voltage for digital inputs/outputs (pin 30) supply voltage for digital section (pin 35) supply voltage for digital part of ADC and DAC (pin 42) total supply current I and Q input voltage symbol rate DAC output current VDD = 5 V CONDITIONS MIN. 4.75 4.75 4.75 4.75 4.75 - - - -100 TYP. 5.0 5.0 5.0 5.0 5.0 30 1.0 - - APPLICATIONS
TDA8041H
* Demodulation of BPSK and QPSK modulated signals in satellite and telephone applications.
MAX. 5.25 5.25 5.25 5.25 5.25 - - 30 x 106 +100 V V V V V
UNIT
mA V symbols/s mA
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8041H Note 1. When using reflow soldering it is recommended that the Drypack instructions in the "Quality Reference Handbook" (order number 9398 510 63011) are followed. QFP44(1) DESCRIPTION plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm; high stand-off height VERSION SOT307-2
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2
November 1994
I ana 18 VDD R4 V ref(pos) V ref(mid) 7 R3 8 R2 Vref(neg) 9 R1 VSS BQN 38 36 37 40
BLOCK DIAGRAM
Philips Semiconductors
handbook, full pagewidth
Quadrature demodulator controller
IDO0 to IDO2 31 to 33 CLK2 A4 3
LCKDAC 44
LCKTC 1
LCKO 2
4 LOGIC I (3..0)
ADC
data LCK LOCK DETECTOR
4 DAC CLK1
I LCK 4 Vref(mid) I CAR DAC CLK1 16 3 15 LCKIO LCKTH CARTC CARO
CARRIER data CAR RECOVERY
4
Vref(mid) 39 V th 14 10 SWPO AFC2O I AFC2 SWEEP
TDA8041H
LOGIC
5 DAC CLK1
AFC2
data AFC2
3
mode control
AFC1 AFC2 TEST
12 AGC data AGC 2 DAC CLK1 I CLK DAC CLK1 CLK2 I bias I bias BIAS GENERATOR I bias ADC DAC OPAMP 26 to 28 QDO0 to QDO2 5 6 11 17 20 24 29 30 CLK1 34 35 42 43 3 CLK1 CLK2 2 25 I AGC 13
AGCTC AGCO
Vref(mid)
21 22 23
19 Q ana
ADC
A4
4 LOGIC
CLOCK data CLK Q (3..0) RECOVERY
5
CLKRTC CLKRO CLKIX
Vref(mid)
41 I bias
CLKSR
Preliminary specification
MBE167
TDA8041H
V SS(A) V SSA(C) V SS1 V DD(I/O) V DDD V SS(C) V DD(A) V SS2 V DDA(C) V SS(I/O) V SSD V DD(C)
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Quadrature demodulator controller
PINNING SYMBOL LCKTC LCKO LCKTH LCKIO VDD(A) VSS(A) Vref(pos) Vref(mid) Vref(neg) AFC2O VSS2 AGCTC AGCO SWPO CARTC CARO VSSA(C) Iana Qana VDDA(C) CLKRTC CLKRO CLKIX PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 DESCRIPTION carrier lock time constant carrier lock output carrier lock threshold voltage carrier lock indicator output supply voltage for operational amplifiers negative supply voltage for operational amplifiers positive reference voltage for converters middle reference voltage for converters negative reference voltage for converters AFC 2 output negative supply voltage 2 automatic gain control time constant automatic gain control output sweep current output carrier recovery time constant carrier recovery output analog negative supply voltage for converters analog input I analog input Q analog supply voltage for converters clock recovery time constant clock recovery output clock input from crystal circuit (at double symbol rate) LCKDAC 44 SWEEP TEST Ibias VDD(C) VSS(C) 39 40 41 42 43 SYMBOL VSS1 CLKSR QDO2 QDO1 QDO0 VSS(I/O) VDD(I/O) IDO2 IDO1 IDO0 VSSD VDDD AFC1 AFC2 BQN PIN 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
TDA8041H
DESCRIPTION negative supply voltage 1 clock output at symbol rate Q digital output (bit 2) Q digital output (bit 1) Q digital output (bit 0) negative supply voltage for digital inputs/outputs supply voltage for digital inputs/outputs I digital output (bit 2) I digital output (bit 1) I digital output (bit 0) negative supply voltage for digital section supply voltage for digital section AFC control switch 1 (1 = on; 0 = off) AFC control switch 2 (1 = on; 0 = off) BPSK/QPSK control switch (1 = BPSK; 0 = QPSK) sweep control switch (1 = on; 0 = off) test control switch (1 = on; 0 = off) input bias current for analog blocks supply voltage for digital part of ADC and DAC negative supply voltage for digital part of ADC and DAC carrier lock DAC output
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Philips Semiconductors
Preliminary specification
Quadrature demodulator controller
TDA8041H
44 LCKDAC
42 VDD(C)
43 VSS(C)
39 SWEEP
35 VDDD
handbook, full pagewidth
LCKTC LCKO LCKTH LCKIO V DD(A) V SS(A) Vref(pos) Vref(mid) Vref(neg) AFC2O V SS2
1 2 3 4 5 6 7 8 9 10 11
34 VSSD
40 TEST
37 AFC2
36 AFC1
41 I bias
38 BQN
33 IDO0 32 IDO1 31 IDO2 30 VDD(I/O) 29 VSS(I/O)
TDA8041H
28 QDO0 27 QDO1 26 QDO2 25 CLKSR 24 VSS1 23 CLKIX
VSSA(C) 17
VDDA(C) 20
CLKRTC 21
AGCTC 12
AGCO 13
SWPO 14
CARTC 15
CARO 16
I ana 18
Q ana 19
CLKRO 22
MBE166
Fig.2 Pin configuration.
November 1994
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Philips Semiconductors
Preliminary specification
Quadrature demodulator controller
GENERAL DESCRIPTION The quadrature demodulator controller TDA8041H, generates all control signals required for demodulation of BPSK and QPSK modulated signals. This device is specially designed to be used in conjunction with the quadrature demodulator IC, TDA8040T. The quadrature demodulator controller generates the following signals: * Symbol clock recovery control signal; this signal locks the VCXO to the received symbol clock. The clock recovery algorithm used in this device operates independently from the other loops. * Carrier recovery control signal; depending on the selected mode (BPSK or QPSK), this signal will adjust the phase of the I and Q input signal. This adjustment will be such that the constellation points are as defined in Fig.4. * Frequency control signals (AFC1 and AFC2); to serve a broad range of applications, two different AFC detectors and a sweep function are built-in: - AFC1: this is a robust detector which forces the offset frequency in the I and Q branch to zero. This detector can handle frequency offset up to 1/8 x symbol rate. - AFC2: this detector can handle frequency offsets greater than 1/8 x symbol frequency. However this AFC algorithm will bring the offset frequency only close to zero. - Sweep: this signal generates a triangular current output which can tune a VCO over its complete frequency range. Sweeping must be switched off as soon as the logical output of the lock detect function becomes positive. The value of the sweep current is set by an external resistor. * Amplitude control signals (AGC); this signal adjusts a variable gain amplifier so that the amplitude of the I and Q signals is in accordance with the specified constellation points of Fig.4. * Lock detect signal; this signal is related to the Eb/No of the incoming I and Q signals. This lock detect signal can be used for two purposes: - Lock detection by comparing the lock detect signal with an external set reference voltage, one can obtain a logical signal indicating lock detect. - The relationship between Eb/No can be used to display the Eb/No for antenna adjustment. Fig.3 FUNCTIONAL DESCRIPTION
TDA8041H
The TDA8041H has a 3-bit-wide digital I and Q output for soft error correction. These 3-bit outputs represent the main symbols only. The relationship between the 4-bits ADC signals and the 3-bit output signals is illustrated in Fig.3.
I and Q output levels for soft error decision FEC.
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Philips Semiconductors
Preliminary specification
Quadrature demodulator controller
TDA8041H
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD(A) VDDA(C) VDD(I/O) VDDD VDD(C) Vn(max) Ptot Tstg Tj Tamb PARAMETER supply voltage for operational amplifiers (pin 5) analog supply voltage for converters (pin 20) supply voltage for digital inputs/outputs (pin 30) supply voltage for digital section (pin 35) supply voltage for digital part of ADC and DAC (pin 42) maximum voltage on all pins total power dissipation storage temperature junction temperature operating ambient temperature Tamb = 70 C CONDITIONS MIN. -0.5 -0.5 -0.5 -0.5 -0.5 0 - -55 - 0 MAX. +6.5 +6.5 +6.5 +6.5 +6.5 VDD 500 +150 +150 +70 V V V V V V mW C C C UNIT
THERMAL CHARACTERISTICS SYMBOL Rth j-a HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. PARAMETER thermal resistance from junction to ambient in free air VALUE 75 UNIT K/W
November 1994
BBBBBB BBBBBB BBBBBBBBBBBBB B BBBBBBBBBBBBB BBBBBBBBBBBBB BBBBBBBBBBBBB BBBBBBBBBBBBB BBBBBBB BBBBBBB BBBBBBB BBBBBBB BBBBBBB BBBBBBB BBBBBBB
Fig.4 Constellation points.
7
Philips Semiconductors
Preliminary specification
Quadrature demodulator controller
CHARACTERISTICS VDD = 4.75 to 5.25 V; Rsym = 30 x 106 symbols/s; Tamb = 25 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. - - - - - - - - - - - - - - - - 0.48VDD 0.38VDD 0.28VDD - - - - - -37 TYP.
TDA8041H
MAX.
UNIT
Digital outputs (pins 26 to 28 and 31 to 33) VOL VOH td th Digital inputs VIL VIH CI VOL VOH Tcy tW tr tf Rsource fs Rsym Vref(pos) Vref(mid) Vref(neg) IL Vi(I,Q) VI,Q(op) RI CI Ibias Io(av) DIo Io LOW level input voltage HIGH level input voltage input capacitance 0 0.7VDD - 0.3VDD VDD 10 V V pF LOW level output voltage HIGH level output voltage delay time hold time see Fig.6 see Fig.6 0 0.9VDD th 8 0.1VDD VDD 22 td V V ns ns
Clock output (pins 22 and 25); see Fig.5 LOW level output voltage HIGH level output voltage cycle time pulse width rise time fall time duty cycle 40/60 CL = 30 pF CL = 30 pF 0 0.9VDD 33 13.2 - - - - - IO = 0 IO = 0 note 1 - - - -5 0 0.28VDD 50 - RL = 100 k VDAC = Vref(mid); note 2 VDAC = Vref(mid); note 2 - - -7 -25 0.1VDD VDD - - 6 6 V V ns ns ns ns MHz
Clock input (pin 23) source resistance sampling frequency 50 60 30 x 106 - - - +5 VDD 0.48VDD - 20 - - +7 +25
Analog inputs (pins 18 and 19) symbol rate positive reference voltage middle reference voltage load current at pin 8 I and Q input voltage I and Q operating voltage input resistance input capacitance input bias current symbols/s V V V mA V V k pF mA
negative reference voltage IO = 0
DAC outputs (pins 10, 12, 15 and 21) average output current matching of positive and negative output currents zero output current 100 - - mA % nA
November 1994
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Philips Semiconductors
Preliminary specification
Quadrature demodulator controller
TDA8041H
SYMBOL Sweep current (pin 14) VOH VOL ZO VCARO(min) VCARO(max) Loop amplifiers Vo Gv GB RL Notes
PARAMETER
CONDITIONS - - SWEEP = 1 SWEEP = 0 - 10
MIN.
TYP. 2Vref(mid) - 0 2 - - - - 60 1 - - - -
MAX.
UNIT
HIGH level output voltage LOW level output voltage output impedance LOW switching level HIGH switching level
V V k M V V
0.1VDD 0.8VDD 0.1VDD -. - 5
0.2VDD 0.9VDD 0.9VDD - - -
output voltage open loop gain gain bandwidth load resistance
V dB MHz k
1. Vref(mid) is usually open-circuit. However, this pin may also be used as a reference output for an external buffer. 2. ( I pos + I neg ) ( I pos - I neg ) I o ( av ) = -------------------------------- ; D lo = 100 x -------------------------------( I pos - I neg ) 2
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Philips Semiconductors
Preliminary specification
Quadrature demodulator controller
TDA8041H
Fig.5 Timing of CLKO.
Fig.6 Timing definition of digital outputs.
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10
dbook, full pagewidth
VSS(C)
VDD(C)
SWEEP
AF C2
AF C1
TEST
VDDD
I bias
BQN
VDDA(C)
VSSA(C)
CLKRTC
SWPO
CARTC
AGCO
Qana
Iana
V SS2 AGCTC 12
CARO
November 1994
10 k 10 k
APPLICATION INFORMATION
Philips Semiconductors
Quadrature demodulator controller
5V 56 k 22 k 8.2 nF 100 nF lock indicator 5V 100 nF 100 nF 100 nF 100 nF
5V
5V
5V 33 nF
100 nF
100 k 43 42 41 40 39 38 37 36 35
100 nF
33 k
44 22 k LCKDAC 1 LCKTC 2 LCKO 3 LCKTH 4 LCKIO 5 6 V SS(A) 7 Vref(pos) 8 Vref(mid) 9 10 AFC2O 11 Vref(neg) V DD(A)
34 VSSD IDO0 IDO1 IDO2 32 31 30 29 28 27 26 25 24 23 5V 10 100 nF 33 I0 I1 I2 5V
VDD(I/O) VSS(I/O)
TDA8041H
QDO0 QDO1 QDO2 CLKSR VSS1 CLKIX CLKRO 22
Q0 Q1 Q2 clock output
11
AFC2 current
13 820 k
14
15 10 nF
16
17
18
19 100 nF
20
21 82 k 10 nF
100 100 nF AGC voltage
270 pF carrier voltage
1 k
330 pF
330 pF
100 pF
27 k 49.7 MHz
4.7 k
50 BFS17A
10 nF
5V I from TDA8040 Q from TDA8040
BB620
10 k
56 pF
0
100 pF
Preliminary specification
390 nH
TDA8041H
56 pF
MBE168
560
10 nF
Fig.7 Application diagram.
Philips Semiconductors
Preliminary specification
Quadrature demodulator controller
PACKAGE OUTLINE
TDA8041H
seating plane
0.15 S
S
12.9 12.3 44 1 34 33 1.2 0.8 (4x)
B
pin 1 index 0.8
11 12 0.40 0.20 10.1 9.9 22
23
0.40 0.20
0.15 M A
1.2 0.8 (4x)
0.15 M B
10.1 9.9
12.9 12.3
X
0.8
A
0.85 0.75 1.85 1.65 0.50 0.20 0.25 0.14 2.35 1.85
MBC864 - 2
detail X
0.95 0.55
0 to 10
o
Dimensions in mm.
Fig.8
Plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm; high stand-off height (QFP44; SOT307-1).
November 1994
12
Philips Semiconductors
Preliminary specification
Quadrature demodulator controller
SOLDERING Plastic quad flat-packs BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 C within 6 s. Typical dwell time is 4 s at 250 C. A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA8041H
applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C. (Pulse-heated soldering is not recommended for SO packages.) For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
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Philips Semiconductors
Preliminary specification
Quadrature demodulator controller
NOTES
TDA8041H
November 1994
14
Philips Semiconductors
Preliminary specification
Quadrature demodulator controller
NOTES
TDA8041H
November 1994
15
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For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 SCD35 (c) Philips Electronics N.V. 1994
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
513161/1500/01/pp16 Document order number: Date of release: November 1994 9397 743 20011
Philips Semiconductors

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